The address bus for a typical memory system carries addresses that are generated by a plurality of drivers, with one of the drivers for each bit in the address. The drivers are switched on and off to generate binary addresses that correspond to selected memory storage locations.
In a block addressable memory array that is suitable for incorporating the present invention, a selected memory storage location in the selected memory array is accessed by addressing the block in which the memory storage location is assigned. The block address is then converted, by suitable gate array logic, into the word address and memory bank selection address that corresponds to the selected memory storage location. The word address is conveyed on the address bus to the memory array.
The address bus is a source of spurious noise because of the switching action of the drivers that supply or feed the address bus. When a new word address is propagated on the address bus, the entire number of drivers may switch simultaneously, if ordinary binary or binary coded decimal codes are used for identification.
Diagnostic operations on the memory array are also difficult to perform with ordinary addressing schemes. This difficulty exists for any address scheme that has a given number of bits because as many as all of the bits may change during a change of address. If an address error occurs with such addressing schemes, it is difficult to attribute the fault to a specific bit or group of bits in the address bus or memory array.